This invention relates to device processing of Silicon-On-Insulator wafers, and more particularly, relates to a method of forming a frontside contact to the silicon substrate of a SOI wafer.
SOI technology has been shown to have many advantages over bulk silicon technology. These advantages include higher speed, lower power and immunity to single event radiation upset. However, there are certain challenges encountered in actual product fabrication of silicon-on-insulator devices. One of these challenges is the need to bias or ground the silicon substrate. In many packaging processes, the substrate is in electrical contact with the package ground. Relying on this approach has several drawbacks such as extra processing must be done to the backside of the wafer to ensure a good electrical contact to the package. In some packaging techniques the silicon chip is flip chip bonded so that the substrate does not make contact with the package ground. In certain instances it is desirable to apply a bias to the substrate which is different than the package ground pin.
The goals of alleviating the drawbacks of not grounding the substrate, providing for ease of contacting the substrate from the frontside of a SOI wafer, and allowing for biasing the substrate through the electrically isolating buried oxide layer has resulted in the present invention.